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PIC32MX3XX/4XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number (1)
64-pin 100-pin
QFN/TQFP TQFP
121-pin
XBGA
Pin
Type
Buffer
Type
Description
TMS
TCK
TDI
TDO
RTCC
CV REF -
CV REF +
CV REFOUT
C1IN-
C1IN+
C1OUT
C2IN-
C2IN+
C2OUT
PMA0
23
27
28
24
42
15
16
23
12
11
21
14
13
22
30
17
38
60
61
68
28
29
34
21
20
32
23
22
33
44
G3
J6
G11
G9
E9
L2
K3
L5
H2
H1
K4
J2
J1
L4
L8
I
I
I
O
O
I
I
O
I
I
O
I
I
O
I/O
ST
ST
ST
—
—
Analog
Analog
Analog
Analog
Analog
—
Analog
Analog
—
TTL/ST
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Real-Time Clock Alarm Output.
Comparator Voltage Reference (low).
Comparator Voltage Reference (high).
Comparator Voltage Reference Output.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered
Slave modes) and Output (Master modes).
PMA1
29
43
K7
I/O
TTL/ST
Parallel Master Port Address Bit 1 Input (Buffered
Slave modes) and Output (Master modes).
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMCS1
PMCS2
8
6
5
4
16
22
32
31
28
27
24
23
45
44
45
44
14
12
11
10
29
28
50
49
42
41
35
34
71
70
71
70
F3
F2
F4
E3
K3
L2
L11
L10
L7
J7
J5
L5
C11
D11
C11
D11
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parallel Master Port Address (De-multiplexed Master
Modes).
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Chip Select 2 Strobe.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1:
Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
? 2010 Microchip Technology Inc.
DS61143G-page 27
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